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ltm4636 -1 1 46361fa for more information www.linear.com/ltm4636-1 typical application description 40a module regulator with overvoltage/ overtemperature protection the lt m ? 4636-1 is a 40a step-down module ? (power module) switching regulator with stacked inductor as a heat sink for heat dissipation and cooler operation in a small package. the ltm4636-1 detects overtemperature and input/output overvoltage conditions and can trip an up - stream power supply or circuit breaker to protect itself and its load. the exposed inductor as a heat sink permits direct contact with airflow from any direction. the ltm4636-1 can deliver 40w (12v in , 1v out , 40a , 200lfm) with only 40c rise over the ambient temperature. full-power 40w is delivered up to 83c ambient and half-power 20w is supported at 110c ambient. the ltm4636 -1 operates at 92%, 90% and 88% efficiency delivering 15a, 30a and 40a , respectively, to a 1v load (12v in ). the module regulator is scalable where four in current sharing deliver 160w with only 40c rise and 88% efficiency (12v in , 1v out , 400lfm). the ltm4636-1 is offered in 16mm 16mm 7.07mm bga package. all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643. 1v, 40a dc/dc module regulator features applications n overtemperature, input/output overvoltage protection n trips upstream power source or circuit breaker n stacked inductor acts as heat sink n wide input voltage range: 4.7v to 15v n 0.6v to 3.3v output voltage range n 1.3% total dc output voltage error ( ? 40 c to 125 c) n differential remote sense amplifier for precision regulation n current mode control/fast transient response n frequency synchronization n parallel current sharing (up to 240a) n 88% efficiency (12v in , 1v out ) at 40a n overcurrent foldback protection n overtemperature shutdown n 16mm 16mm 7.07mm bga package n telecom servers and networking equipment n industrial equipment and medical systems 12v in , 1v out efficiency at 350khz vs output current output current (a) 0 efficiency (%) 90 95 100 15 25 46361 ta01b 85 80 5 10 20 30 40 35 75 70 see the ltm4636 for simpler circuit and fewer features. temp + temp ? sgnd v in 1v 34.8k 22f 0.1f 22f 16v 5 4.7v to 15v v sys 4.5v to 5.5v range 100f 25v intv cc pv cc v in 5.5v, tie v in and pv cc together, tie runp to gnd. v in > 5.5v, then operate as shown optional temp monitor intv cc intv cc pv cc ltm4636-1 pv cc pgnd v outs1 + v out otp_set ovp_set crowbar optional crowbar v outs1 ? v fb bias bias + 470f 6.3v 3 + 7.5k 100f 6.3v 4 v out 1v, 40a 46361 ta01a pins not used in this circuit: clkout, gmon, pgood, phmode, pwm, sw, test1, test2, test3, tmon compa compb snsp1 snsp2 mode/pllin track/ss 15k runc runp hizreg ovp_trip over_temp freq hot swap circuit breaker upstream bias regulator optional overtemperature and overvoltage fault signal 61.9k 86.6k 0.01f 100k
ltm4636 -1 2 46361fa for more information www.linear.com/ltm4636-1 absolute maximum ratings v in , sw, hzbreg, runp, ovr_trip , over temp ............................................... ? 0.3v to 16v v out .......................................................... ? 0.3v to 3.5v pgood, runc, tmon, pv cc , mode/pllin, phmode, freq, track/ss, test1, test2, v out s1 ? , v out s1 + , sns p1 , sns p2 , test3, ov p_ se t , crowbar .................... ? 0.3v to intv cc ( 5v ) v fb , compa, compb (note 6) .................. ? 0.3v to 2.7v bias ............................................................. ? 0.3v to 6v (note 1) order information lead free finish tray part marking* package description temperature range ltm4636-1ey#pbf ltm4636-1ey#pbf ltm4636-1 144-lead (16mm 16mm 7.07mm) bga ?40c to 125c ltm4636-1iy#pbf ltm4636-1iy#pbf ltm4636-1 144-lead (16mm 16mm 7.07mm) bga ?40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ pin configuration 1 m l k j h g f e d c b a top view bga package 144-lead (16mm 16mm 7.07mm) v out gnd gnd gnd gnd sw v in 2 3 4 5 6 7 8 9 10 11 12 pgood runc snsp2 snsp1 compb test2 crowbar ovp_trip over_temp otp_set intv cc temp ? ovp_set temp + clkout sgnd v fb v outs1 + hizreg track/ss compa v outs1 ? freq pwm test3 mode/pllin test1 tmon bias gmon phmode runp pv cc t jmax = 125c, ja = 7.5c/w, jcbottom = 3c/w, jctop = 15c/w, jba = 12c/w ja = derived from 95mm 76mm pcb with 6 layers, weight = 3.95g values determined per jesd51-12 note: ja = ( jcbottom + jba )|| jctop ; jba is board to ambient pv cc additional output current ................ 0ma to 50ma temp + , temp ? .......................................... ? 0.3v to 0.8v intv cc peak output current (note 6) .................... 20ma internal operating temperature range (note 2) .................................................. ? 40 c to 125 c storage temperature range .................. ? 55 c to 125 c reflow (peak body) temperature .......................... 250 c note : pwm, clkout, and gmon are outputs only. http://www.linear.com/product/ltm4636-1#orderinfo
ltm4636 -1 3 46361fa for more information www.linear.com/ltm4636-1 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 12v, per the typical application in figure 20. symbol parameter conditions min typ max units v in input dc voltage v in 5.5v, tie v in and pv cc together, tie runp to gnd l 4.70 15 v v out v out range l 0.6 3.3 v v out(dc) dc output voltage, total variation with line and load c in = 22f 5 c out = 100f 4 ceramic, 470f poscap 3 r fb = 40.2k, mode_pllin = gnd v in = 4.70v to 15v, i out = 0a to 40a (note 4) l 1.4805 1.50 1.5195 v input specifications v runc runc pin on threshold v runc rising 1.1 1.22 1.35 v v runchys runc pin on hysteresis 150 mv v runp runp pin on threshold runp pin rising l 0.7 0.8 0.9 v runp hys runp pin hysteresis 60 mv hizreg hizreg input threshold v in = 12v, runc = 5v, runp = v in , v out = 1.5v 2.3 v hizreg hys hizreg hysteresis v in = 12v, runc = 5v, runp = v in , v out = 1.5v 0.8 v i q(vin) input supply bias current v in = 12v, v out = 1.5v, burst mode operation, i out = 0.1a v in = 12v, v out = 1.5v, pulse-skipping mode, i out = 0.1a v in = 12v, v out = 1.5v, switching continuous, i out = 0.1a shutdown, run = 0, v in = 12v 16 23 105 30 ma ma ma a i s(vin) input supply current v in = 5v, v out = 1.5v, i out = 40a v in = 12v, v out = 1.5v, i out = 40a 14.7 5.66 a a output specifications i out(dc) output continuous current range v in = 12v, v out = 1.5v (note 4) 0 40 a ?v out (line) v out line regulation accuracy v out = 1.5v, v in from 4.70v to 15v i out = 0a l 0.02 0.06 %/v ?v out (load) v out load regulation accuracy v out = 1.5v, i out = 0a to 40a, v in = 12v (note 4) l 0.2 0.35 % v out(ac) output ripple voltage i out = 0a, c out = 100f 3 ceramic, 470f 3 poscap, v in = 12v, v out = 1.5v 15 mv p-p ?v out(start) turn-on overshoot c out = 100f 4 ceramic, 470f 3 poscap, v out = 1.5v, i out = 0a, v in = 12v, track/ss = 0.1f 5 mv t start turn-on time c out = 100f 3 ceramic, 470f 3 poscap, no load, track/ss = 0.001f, v in = 12v 750 s ?v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 100f 4 ceramic, 470f 3 poscap, v in = 12v, v out = 1.5v, cff = 22pf 45 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 5v, c out = 100f 4 ceramic, 470f 3 poscap, v in = 12v, v out = 1.5v, cff = 22pf 25 s i outpk output current limit v in = 12v, v out = 1.5v v in = 5v, v out = 1.5v 54 54 a a control section v fb voltage at v fb pin i out = 0a, v out = 1.5v l 0.594 0.600 0.606 v i fb current at v fb pin (note 6) ?30 ?100 na v ovl feedback overvoltage lockout measure at v outs1 l 5 7.5 10 % i track/ss track pin soft-start pull-up current track/ss = 0v, default 750s turn on with track/ss tied to intv cc 1.1 1.35 1.6 a t on(min) minimum on-time (note 3) 100 ns r fbhi resistor between v outs1 and v fb pins 4.99 k
ltm4636 -1 4 46361fa for more information www.linear.com/ltm4636-1 symbol parameter conditions min typ max units remote sense amplifier a v(vfb) v fb differential gain (note 6) 1 v/v gbp v fb path gain bandwidth product (note 5) 4 mhz general control or monitor pins ovp ?t ovp to ovp_trip ovp response time 500 ns crowbar ?t ovp to crowbar ovp response time to crowbar 500 ns ovp delay ovp to over_temp ovp_temp to ovp_temp response time 8 s ovp_trip sink ovp_trip sink current v ce 0.4v 15 ma otp_trip sink over_temp sink current v ce 0.4v 15 ma crowbar source crowbar source current v crowbar 3.0v 15 ma otp_set overtemperature set register 24.9 k ovp_set overvoltage set register 24.9 k i tmon temperature monitor current, t j = 25c into 24.9k temperature monitor current, t j = 150c into 24.9k 38 40.3 58 44 a a i tmon(slope) temperature monitor current slope, r tmon = 24.9k 0.144 a/c v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive ?7.5 7.5 % % v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v t pgood v pgood high-to-low delay 65 s i pgood(off) pgood leakage current v pgood = 5v ?2 2 a v pg1(hyst) pgood trip level hysteresis 2.5 % intv cc linear regulator v intvcc internal v cc voltage source 6v < v in < 15v 5.3 5.5 5.7 v v intvcc load reg intv cc load regulation i cc = 0ma to 10ma 0.5 % uvlo hys controller uvlo hysteresis (note 6) 0.5 v pv cc(uvlo) drivers and power mosfets uvlo pv cc rising 3.5 3.8 4.1 v pv cc(hys) pv cc uvlo hysteresis 0.45 v pv cc power stage bias 12v input, pv cc load = 50ma 5.0 v bias external bias for otp and ovp function range operating 4 5.0 5.5 v electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 12v, per the typical application in figure 20.
ltm4636 -1 5 46361fa for more information www.linear.com/ltm4636-1 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 12v, per the typical application in figure 20. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4636-1 is tested under pulsed load conditions such that t j t a . the ltm4636-1e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full ?40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4636-1i is guaranteed to meet specifications over the full ?40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of i max load. (see the applications information section) note 4: see output current derating curves for different v in , v out and t a . note 5: guaranteed by design. note 6: 100% tested at wafer level. symbol parameter conditions min typ max units oscillator and phase-locked loop f osc oscillator frequency v phsmd = 0v r freq = 30.1k r freq = 47.5k r freq = 54.9k r freq = 75.0k maximum frequency minimum frequency l l 210 540 625 945 1.2 250 600 750 1.05 290 660 825 1.155 0.2 khz khz khz mhz mhz mhz i freq freq pin output current v freq = 0.8v 19 20 21 a r mode/pllin mode_pllin input resistance 250 k v mode/pllin pllin input threshold v mode/pllin rising v mode/pllin falling 2 1.2 v v v clkout low output voltage high output voltage verified levels measurements on clkout 0.2 5.2 v v pwm-clkout pwm to clockout phase delay v phmode = 0v v phmode = 1/4 intv cc v phmode = float v phmode = 3/4 intv cc v phmode = intv cc 90 90 120 60 180 deg deg deg deg deg pwm/pwmen outputs pwm pwm output high voltage i load = 500a 5.0 v pwm output low voltage i load = ?500a 0.5 v temperature diode diode v f diode forward voltage i = 100a, temp + to temp ? 0.598 v tc temperature coefficient l ?2.0 mv/ c
ltm4636 -1 6 46361fa for more information www.linear.com/ltm4636-1 typical performance characteristics 2.5v transient response 1.5v transient response 1.8v transient response 12v to 1.5v transient response c out = 4 100f ceramic, 3 470f 2.5v poscap 5m c ff = 22pf, sw freq = 425khz c comp = 100pf 10a/div 18a/s step 50mv/div 50s/div 46361 g07 12v to 1.8v transient response c out = 6 100f ceramic, 2 470f 4v poscap 5m c ff = 22pf, sw freq = 500khz c comp = 100pf 10a/div 18a/s step 50mv/div 100s/div 46361 g08 12v to 2.5v transient response c out = 6 100f ceramic, 2 470f 4v poscap 5m c ff = 22pf, sw freq = 650khz c comp = 100pf 10a/div 18a/s step 100mv/div 100s/div 46361 g09 burst mode efficiency vs load current 1v transient response 1.2v transient response efficiency vs load current with 5v in efficiency vs load current with 8v in efficiency vs load current with 12v in output current (a) 0 efficiency (%) 100 90 80 95 85 75 70 25 15 35 46361 g01 40 20 105 30 3.3v out , 500khz 2.5v out , 500khz 1.8v out , 450khz 1.5v out , 425khz 1.2v out , 300khz 1v out , 300khz output current (a) 0 efficiency (%) 100 90 80 95 85 75 70 25 15 35 46361 g02 40 20 105 30 3.3v out , 700khz 2.5v out , 600khz 1.8v out , 500khz 1.5v out , 450khz 1.2v out , 400khz 1v out , 350khz output current (a) 0 efficiency (%) 100 90 80 95 85 75 70 25 15 35 46361 g03 40 20 105 30 3.3v out , 750khz 2.5v out , 650khz 1.8v out , 600khz 1.5v out , 550khz 1.2v out , 400khz 1v out , 350khz output current (a) 0 efficiency (%) 100 80 60 90 70 50 40 32 4 46361 g04 5 1 burst mode operation v in 12v v out 1.5v 12v to 1v transient response c out = 4 100f ceramic, 3 470f 2.5v poscap 5m c ff = 22pf, sw freq = 400khz 10a/div 18a/s step 50mv/div 50s/div 46361 g05 12v to 1.2v transient response c out = 4 100f ceramic, 3 470f 2.5v poscap 5m c ff = 22pf, sw freq = 400khz c comp = 100pf 10a/div 18a/s step 50mv/div 50s/div 46361 g06
ltm4636 -1 7 46361fa for more information www.linear.com/ltm4636-1 typical performance characteristics 3.3v transient response 40a load short-circuit start-up with soft-start no-load start-up with 0.5v output pre-bias start-up with soft-start full load no-load short-circuit run pin capacitor = 0.1f track/ss capacitor = 0.1f c out = 4 100f ceramic and 3 470f poscap 20ms/div v in 5v/div v out 0.5v/div 46361 g11 run pin capacitor = 0.1f track/ss capacitor = 0.1f c out = 4 100f ceramic and 3 470f poscap 20ms/div v in 5v/div v out 0.5v/div 46361 g12 100s/div l in 200ma/div v out 0.5v/div 46361 g13 run pin capacitor = 0.1f track/ss capacitor = 0.1f c out = 4 100f ceramic and 3 470f 20ms/div v in 5v/div v out 0.5v/div 46361 g14 100s/div l in 200ma/div v out 0.5v/div 46361 g15 12v to 3.3v transient response c out = 6 100f ceramic, 2 470f 4v poscap 5m c ff = 22pf, sw freq = 750khz c comp = 100pf 10a/div 18a/s step 100mv/div 100s/div 46361 g10
ltm4636 -1 8 46361fa for more information www.linear.com/ltm4636-1 pin functions v out ( a1- a12, b1 - b12, c1 - c12, d1 - d2, d11 - d12 ): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance between these pins and gnd pins. review table 4. mode_pllin ( h3 ): forced continuous mode, burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to intv cc to enable pulse-skipping mode of operation. connect to ground to enable forced continuous mode of operation. floating this pin will enable burst mode operation. a clock on this pin will enable synchronization with forced continuous operation. see the applications information section. v outs1 ? (d3): v out sense ground for the remote sense amplifier. this pin connects to the ground remote sense point. connect to ground when not used. see the applica - tions information section. v outs1 + (d4): this pin should connect to v out and is connected to v fb through a 4.99k resistor. this pin is used to connect to a remote sense point of the load for accurate voltage sensing. either connect to remote sense point or directly to v out . see the applications information section for details. compb (d5 ): internal compensation network provided that coincides with proper stability utilizing the values in table 5. just connect this pin to compa for internal compensa - tion. in parallel operation with other ltm4636-1 devices, connect compa and compb pins together for internal compensation, then connect all compa pins together. gnd ( d6-d9, e6-e9, f7, f8, f10, f12, g1-g2, g6 g10, h1, h10 - h12, j1 - j3, j8 - j12, k1 - k3, k9 - k10, k12, l1 - l3, l9-l10, l12, m1-m3, m9-m12): ground pins for both input and output returns. pgood (e1): output voltage power good indicator. open- drain logic output is pulled to ground when the output voltage exceeds a 7.5% regulation window. runc (e2): run control pin. a voltage above 1.35v will turn on the control section of the module. a 10k resistor to ground is internal to the module for setting the run pin threshold with a resistor to 5v, and allowing a pull- up resistor to pv cc for enabling the device. see figure 1 block diagram. track/ss (e3 ): output voltage tracking pin and soft-start inputs. the pin has a 1.25a pull-up current source. a capacitor from this pin to ground will set a soft-start ramp rate. in tracking, the regulator output can be tracked to a different voltage. the different voltage is applied to a voltage divider then to the slave output?s track pin. this voltage divider is equal to the slave output?s feedback divider for coincidental tracking. default soft-start of 750s with track/ss pin connected to intv cc pin. see the applica - tions information section. in polyphase ? applications tie the track/ss pins together. v fb (e4): the negative input of the error amplifier. inter - nally, this pin is connected to v outs1 with a 4.99k precision resistor. different output voltages can be programmed with an additional resistor between v fb and v osns ? . in polyphase operation, tying the v fb pins together allows for parallel operation. see the applications information section. compa ( e5 ): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. tie all compa pins together for parallel operation. this pin allows external compensation. see the applications information section. ovp_trip (e10): this open-drain pin can be used to trip off and retry an input circuit breaker or alert the system to an output overvoltage programmed on the ovp_set pin. see the applications information section. crowbar (e11): this pin can be optionally used to clamp the output voltage in an overvoltage condition to protect the load to tighter control of overvoltage. see the applications information section. snsp2 (f1): current sense signal path. connect this pin to snsp1 (f2). snsp1 (f2): current sense signal path. connect this pin to snsp2 (f1). both pins are used to calibrate current sense matching and current limit at final test. package row and column labeling may vary among module products. review each package layout carefully.
ltm4636 -1 9 46361fa for more information www.linear.com/ltm4636-1 pin functions hizreg (f3): when this pin is pulled low the power stage is disabled into high impedance. tie this pin to v in or intv cc for normal operation. over_temp (d10): this overtemperature protection is programmable with an internal monitor that is referenced to the tmon pin and the otp_set pin. the over_temp pin can be used to alert the system if the module regulator overheats, and this signal can be used to trip off and retry an electronic circuit breaker in a fault condition. the pin is an open collector that pulls active low in response to over_temp. the over_temp pin can be left floating if not used. see the applications information section for details. sgnd ( f4, g4): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the application. see layout guidelines in figure 18. intv cc (f6): internal 5.5v ldo for driving the control circuitry in the ltm4636 -1. intv cc is controlled and enabled when runc is activated high. freq (g5): a resistor can be applied from this pin to ground to set the operating frequency. this pin sources 20a. see the applications information section. phmode (g7 ): this pin can be voltage programmed to change the phase relationship of the clkout pin with refer - ence to the internal clock or an input synchronized clock. the intv cc ( 5.5v ) output can be voltage divided down to the phasmd pin to set the particular phase. the electri - cal characteristics show the different settings to select a particular phase. see the applications information section. runp (g8): this pin enables the pv cc supply. this pin can be connected to v in , or tie to ground when connecting pv cc to v in 5.5v . runp needs to sequence up before runc. a 15k resistor from pv cc to runc with a 0.1f capacitor will provide enough delay. in parallel operation with multiple ltm4636-1s, the resistor can be reduced in value by n times and the 0.1f can be increased n times. see applications information section. runp can be used to set the minimum uvlo with a voltage divider. see figure 1. pv cc (f9): 5v power output and power for internal power mosfet drivers. the regulator can power 50ma of external sourcing for additional use. place a 22f ceramic filter capacitor on this pin to ground. when v in < 5.5v , tie v in and pv cc together. then tie runp to gnd. if v in > 5.5v then operate pv cc regulator as normal. see the typical application examples. ovp_set ( e12 ): this pin is used to set the output overvolt - age trip point. this pin has a 24.9k resistor on it to ground. see the applications information section. float is not used. bias (g9): this pin is used to power the otp and ovp circuitry independently of the main power feed. see the applications information section. temp + (g12): temperature monitor. an internal diode connected npn transistor. see the applications informa - tion section. otp_set ( f11 ): this pin is used to set the overtemperature set point. the pin has a 24.9k resistor on it to ground. see applications information section. float if not used. temp ? (g11): low side of the internal temperature monitor. clkout (g3): clock out signal that can be phase selected to the main internal clock or synchronized clock using the phasmd pin. clkout can be used for multiphase applications. see the applications information section. test1 (h4), test2 (f5), test3 (h2), gmon (h9):these are test pins used in the final production test of the part. leave floating. v in ( h5-h6, j4-j7, k4-k8, l4-l8, m4-m8): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in and gnd pins. pwm ( h7 ): pwm output that drives the power stage. primar - ily used for test, but can be monitored in debug or testing. tmon (h8 ): temperature monitor pin. internal temperature monitor, varies from 1.0v at 25 c to 1.44v at 150 c , disables power stage at > 150 c . the otp_trip signal is set to trip off at a value lower than 150 c . if the temperature moni - tor feature is not desired, then tie the tmon pin to gnd. sw ( l11, k11): these are pin connections to the internal switch node for test evaluation and monitoring. an r-c snubber can be placed from the switch pins to gnd to eliminate any high frequency ringing. see the applications information section.
ltm4636 -1 10 46361fa for more information www.linear.com/ltm4636-1 block diagram figure 1. simplified ltm4636-1 block diagram pgood + tdrv pwm input 150c disable disable temp monitor current imon 40a at 25c 60a at 150c pwm logic contol, power mosfet drivers, power mosfet m1 0.18h snsp2 sns ? bdrv m2 24.9k 1% 4.99k 0.5% 0.1f 10pf 0.1f soft-start 10k 1% uvlo example > 1.35v = on 15k = (pv cc ? 1.35v)(10k)/1.35v disables at ~ 3.75v pvcc = 5v 15k 10k intv cc pv cc snsp1 snsp1 and snsp2 connected at pcb sns ? 470pf q1 1f 22f optional v in pv cc > 0.85v = on internal 5v regulator 2.2 2.2f 2.2, 0805 sgnd snsp2 connect to snsp1 temp ? gmon tmon pwm v outs1 ? temp ? temp + gnd v out v out 1.5v at 40a sw v in v in 4.70v to 15v v in 5.5v, tie to v in and pv cc together, tie runp to gnd. v in > 5.5v operate as shown v in uvlo example c in runp r1 pv cc optimized dead time control dcr sense network 5v v outs1 + + ? v fb diff amp current sense pwm power control freq track/ss v fb r6 3.24k mode_pllin intvcc 5.5v snsp1 phmode hizreg intv cc clkout sgnd compb compa runc test3 test2 test1 test4 r freq 40k tmon bias otp_set 46361 f01 over_temp + ? + c out 4.7f internal comp 1f 2200pf 15k r1 = (v in ? 0.85v) (15k) 0.85v 24.9k 1% ? + 220pf bias ovp_set ovp_trip bias 24.9k 1% v out + ? crowbar tmon
ltm4636 -1 11 46361fa for more information www.linear.com/ltm4636-1 decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.70v to 16v , v out = 1.5v ) i out = 40a, 6 22f ceramic x7r capacitors (see table 4) 100 f c out external output capacitor requirement (v in = 4.70v to 16v , v out = 1.5v ) i out = 40a (see table 4) 1000 f t a = 25 c. use figure 1 configuration. power module description the ltm4636 -1 is a high efficiency regulator that can provide a 40a output with few external input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 3.3v dc over a 4.70v to 15v input range. the typical application schematic with protection is shown in figure 20. the ltm4636 -1 has an integrated constant-frequency current mode regulator, power mosfets, 0.18h induc - tor, protection circuitry, 5v regulator and other supporting discrete components. the switching frequency range is from 250khz to 770khz , and the typical operating frequency is 400khz . for switching noise-sensitive applications, it can be externally synchronized from 250khz to 800khz, subject to minimum on-time limitations and limiting the inductor ripple current to less than 40% of maximum output current. a single resistor is used to program the frequency. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4636-1 module has sufficient sta - bility margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. an option has been provided for external loop compensation. ltpowercad ? can be used to optimize the external compensation option. see the applications information section. current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. an internal overvoltage monitor feedback pin referred will attempt to protect the output voltage in the event of an overvoltage >10%. the top mosfet is turned off and the bottom mosfet is turned on until the output is cleared. operation pulling the runc pin below 1.1v forces the regulator con- troller into a shutdown state. the track/ss pin is used for programming the output voltage ramp and voltage tracking during start-up. see the applications information section. optional internal overvoltage protection and overtem - perature functions can be used to protect from power mosfet failures, input and output overvoltage and over - temperature conditions. these two features can be used to trip off and retry an input circuit breaker in the event of either/or both an overvoltage and overtemperature fault. the ovp_trip, over_temp, tmon, ovp_set, crowbar and otp_set pins are all used to support these two features. these features can be implemented along with an input circuit breaker to protect expensive systems boards, processors and fpga devices from damage. see the applications information section. the ltm4636 -1 is internally compensated to be stable over all operating conditions. table 5 provides a guideline for input and output capacitances for several operating conditions. ltpowercad is available for transient and stability analysis. this tool can be used to optimize the regulators loop response. a remote sense amplifier is provided for accurately sensing output voltages at the load point. multiphase operation can be easily employed with the internal clock source or a synchronization clock applied to the mode/pllin input using an external clock source, and connecting the clkout pins. see the applications information section. review figure 4. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode_pllin pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load op - eration in the typical performance characteristics section.
ltm4636 -1 12 46361fa for more information www.linear.com/ltm4636-1 operation a temp + and temp ? pins are provided to allow the internal device temperature to be monitored using an onboard diode connected npn transistor. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode_pllin pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load op - eration in the typical performance characteristics section. applications information the typical ltm4636 -1 application circuit is shown in figure 20. external component selection is primarily determined by the maximum load current and output voltage. refer to table 5 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the v in to v out step-down ratio that can be achieved for a given input voltage. the maximum duty cycle is 94% typical at 500khz operation. the v in to v out minimum dropout is a function of load current and operation at very low input voltage and high duty cycle applications. at very low duty cycles the minimum 100ns on-time must be maintained. see the pll, frequency adjustment and synchronization section and temperature derating curves. output voltage programming the pwm controller has an internal 0.6v 1% reference voltage. as shown in the block diagram, a 4.99k internal feedback resistor connects the v outs1 and v fb pins to- gether. when the remote sensing is used, then v outs1 + and v outs1 ? are connected to the remote v out and gnd points. if no remote sense the v outs1 + connects to v out . the output voltage will default to 0.6v with no feedback resistor. adding a resistor r fb from v fb to ground programs the output voltage: v out 0.6v ? 4.99k r fb r fb table 1. v fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 r fb (k) open 7. 5 4.99 3.24 2.49 1.58 1.1 for parallel operation of n ltm4636-1s, the following equation can be used to solve for r fb : r fb 4.99k / n v out 0.6v ? 1 or use v outs1 on one channel and connect all feedback pins together utilizing a single feedback resistor. tie the v fb pins together for each parallel output. the comp pins must be tied together also. see the typical applications section examples. input capacitors the ltm4636 -1 module should be connected to a low ac-impedance dc source. additional input capacitors are needed for the rms input ripple current rating. the i cin(rms) equation which follows can be used to calculate the input capacitor requirement. typically 22f x7r ceramics are a good choice with rms ripple current ratings of ~4a each. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty cycle can be estimated as: d v out v in
ltm4636 -1 13 46361fa for more information www.linear.com/ltm4636-1 applications information without considering the inductor ripple current, for each output the rms current of the input capacitor can be estimated as: i cin(rms) i out(max) % ? d ? (1? d) where % is the estimated efficiency of the power mod- ule. the bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a polymer capacitor. output capacitors the ltm4636 -1 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitors. the typi- cal output capacitance range is from 400f to 1000f. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 5 shows a matrix of dif - ferent output voltages and output capacitors to minimize the voltage droop and overshoot during a 15a/s tran - sient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 5 matrix, and ltpowercad is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancel - lation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad can be used to calculate the output ripple reduction as the number of implemented phases increases by n times. external loop compensation can be used for transient response optimization. burst mode operation the ltm4636 -1 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for ap - plications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply float the mode_pllin pin. during burst mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the compa pin indicates a lower value. the voltage at the compa pin drops when the inductor?s average current is greater than the load requirement. as the compa voltage drops below 0.5v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. the load current is now being supplied from the output capacitors. when the output voltage drops, causing compa to rise, the internal sleep line goes low, and the ltm4636-1 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high effi - ciency at intermediate currents are desired, pulse-skipping mode should be used. pulse-skipping operation allows the ltm4636 -1 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. with pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. this mode has lower ripple than burst mode operation and maintains a higher frequency operation than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to ground. in this mode, inductor current is allowed to reverse during low output loads, the compa voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4636-1?s output voltage is in regulation.
ltm4636 -1 14 46361fa for more information www.linear.com/ltm4636-1 multiphase operation for outputs that demand more than 40a of load current, multiple ltm4636 -1 devices can be paralleled to provide more output current without increasing input and output ripple voltage. the mode_pllin pin allows the ltm4636 -1 to be synchronized to an external clock and the internal phase-locked loop allows the ltm4636-1 to lock onto input clock phase as well. the freq resistor is selected for normal frequency, then the incoming clock can syn - chronize the device over the specified range. a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. see application note 77. the ltm4636 -1 device is an inherently current mode controlled device, so parallel modules will have good cur - rent sharing. this will balance the thermals in the design. tie the compa to compb and then tie the compa pins together, tie v fb pins of each ltm4636-1 together to share the current evenly. figure 21 shows a schematic of the parallel design. for external compensation and parallel operation only tie comp a pins together with external compensation. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases (see figure 2). pll, frequency adjustment and synchronization the ltm4636 -1 switching frequency is set by a resistor (r freq ) from the freq pin to signal ground. a 20a current (i freq ) flowing out of the freq pin through r freq develops a voltage on the freq pin. r freq can be calculated as: r freq freqv 20a applications information figure 2. normalized input rms ripple current vs duty cycle for one to six module regulators (phases) 0.75 0.8 46361 f02 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty cycle (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1 phase 2 phase 3 phase 4 phase 6 phase
ltm4636 -1 15 46361fa for more information www.linear.com/ltm4636-1 the relationship of freqv voltage to switching frequency is shown in figure 3. for low output voltages from 0.6v to 1.2v, 350khz operation is an optimal frequency for the best power conversion efficiency while maintaining the inductor current to about 45% of maximum load current. for output voltages from 1.5v to 1.8v, 500khz is optimal. for output voltages from 2.5v to 3.3v, 700khz is optimal. see efficiency graphs for optimal frequency set point. limit the 2.5v and 3.3v outputs to 35a. the ltm4636 -1 can be synchronized from 200khz to 1200khz with an input clock that has a high level above 2v and a low level below 1.2v . see the typical applications section for synchronization examples. the ltm4636-1 minimum on-time is limited to approximately 100ns. the on-time can be calculated as: t on(min) 1 freq ? v out v in applications information the ltm4636 -1's clkout pin phase difference from v out can be programmed by applying a voltage to the phmode pin. this voltage can be programmed using the 5.5v intv cc pin. most of the phase selections can be programmed by either grounding, floating, or tying this pin to intv cc . the 60 degree phase shift will require 3/4 intv cc and can be programmed with a voltage divider from the intv cc pin. see figure 4 for phase programming and the 2 to 6 phase connections. see figure 21 for example design. output voltage tracking output voltage tracking can be programmed externally using the track /ss pin. the output can be tracked up and down with another regulator. the master regulator ?s output is divided down with an external resistor divider that is the same as the slave regulator?s feedback divider to implement coincident tracking. the ltm4636-1 uses figure 3. freq voltage to switching frequency v freq (v) 0.4 frequency (khz) 900 1100 1300 1.0 1.4 46361 f03 700 500 0.6 0.8 1.2 1.6 1.8 300 100
ltm4636 -1 16 46361fa for more information www.linear.com/ltm4636-1 applications information an accurate 4.99k resistor internally for the top feedback resistor. figure 5 shows an example of coincident tracking. v out(slave) 1 4.99k r ta ? v track v track is the track ramp applied to the slave?s track pin. v track has a control range of 0v to 0.6v, or the internal reference voltage. when the master?s output is divided down with the same resistor values used to set the slave ?s output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slave ? s regulation point (see figure 6). voltage tracking is disabled when v track is more than 0.6v. r ta in figure 5 will be equal to r fb for coincident tracking. the track /ss pin of the master can be controlled by an external ramp or the soft-start function of that regulator can be used to develop that master ramp. the ltm4636-1 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. a 1.25a current source is used to charge the soft-start capacitor. the following equation can be used: t soft-start 0.6v ? c ss 1.25a figure 4. phase selection examples ltm4636-1 180 phase mode_pllin phmode clkout v out 3/4 intv cc ltm4636-1 240 phase mode_pllin phmode clkout v out 3/4 intv cc ltm4636-1 300 phase mode_pllin phmode 46361 f04 clkout v out 3/4 intv cc ltm4636-1 0 phase mode_pllin phmode r2 10k r1 30.1k clkout v out ltm4636-1 0 phase mode_pllin phmode clkout v out ltm4636-1 90 phase mode_pllin phmode clkout v out ltm4636-1 180 phase mode_pllin phmode clkout v out ltm4636-1 270 phase mode_pllin phmode clkout v out 3/4 intv cc intv cc ltm4636-1 60 phase six phase four phase ltm4636-1 0 phase mode_pllin phmode clkout v out ltm4636-1 120 phase mode_pllin phmode clkout v out ltm4636-1 240 phase mode_pllin phmode clkout v out three phase ltm4636-1 0 phase mode_pllin phmode clkout v out ltm4636-1 180 phase mode_pllin phmode clkout v out float intv cc two phase mode_pllin phmode clkout v out 3/4 intv cc ltm4636-1 120 phase mode_pllin phmode clkout v out 3/4 intv cc v out phase 0 0 0 0 0 clkout phase 90 90 120 60 180 phmode (v) 0 1/4 intv cc float 3/4 intv cc intv cc phase selection
ltm4636 -1 17 46361fa for more information www.linear.com/ltm4636-1 applications information figure 5. dual outputs (1.5v and 1.2v) with tracking figure 6. output voltage coincident tracking characteristics 46361 f06 time slave output master output output voltage + compa compb track/ss runc runp hizreg freq tmon sw v out temp + temp ? snsp1 snsp2 sgnd v in 15k 5v pv cc1 1.5v at 40a 2.2, 0805 2200pf 40.2k c ss 0.1f 22f voltage out temp monitor 0.1f 22f 16v 5 4.7v to 15v 100f 25v intv cc1 optional temp monitor for telemetry readback ics intv cc intv cc1 5v pv cc1 ltm4636-1 pv cc pgnd v outs1 + v outs1 ? v fb + 470f 6.3v 470f 6.3v + + 470f 6.3v r fb 3.24k 100f 4 6.3v 46361 f05 + compa compb track/ss runc runp hizreg freq tmon sw v out temp + temp ? snsp1 snsp2 sgnd v in 15k 1.5v 5v pv cc2 1.2v at 40a r7b 4.99k r7a 4.99k 22f voltage out temp monitor 0.1f 22f 16v 5 intv cc2 optional temp monitor for telemetry readback ics intv cc intv cc2 5v pv cc2 ltm4636-1 pv cc pgnd v outs1 + v outs1 ? v fb 470f 6.3v 470f 6.3v + + 470f 6.3v r fb1 4.99k 100f 4 6.3v 2.2, 0805 2200pf pins not used in this circuit: clkout, gmon, mode/pllin, pgood, otp_set, crowbar, ovp_trip, ovp_set, bias, over_temp, phmode, pwm, test1, test2, test3
ltm4636 -1 18 46361fa for more information www.linear.com/ltm4636-1 applications information ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master ?s track/ss pin. as mentioned above, the track/ss pin has a control range from 0v to 0.6v. the master ?s track/ss pin slew rate is directly equal to the master?s output slew rate in volts/time. the equation: mr sr ? 4.99k r tb where mr is the master ? s output slew rate and sr is the slave? s output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal to 60.4k. r ta is derived from equation: r ta 0.6v v fb 4.99k v fb r fb1 ? v track r tb where v fb is the feedback voltage reference of the regula - tor, and v track is 0.6v . since r tb is equal to the 4.99k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 4.99k , and r ta = 4.99k in figure 5. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. for example, mr = 1.5v/ms, and sr = 1.2v/ms. then r tb = 6.19k. solve for r ta to equal 4.22k. for applications that do not require tracking or sequenc - ing, simply tie the track/ss pin to intv cc to let run control the turn on/off. when the run pin is below its threshold or the v in undervoltage lockout, then track/ss is pulled low. default overcurrent and overvoltage protection the ltm4636 -1 has overcurrent protection (ocp) in a short circuit. the internal current comparator threshold folds back during a short to reduce the output current. an overvoltage condition (ovp) above 10% of the regulated output voltage will force the top mosfet off and the bottom mosfet on until the condition is cleared. foldback current limiting is disabled during soft-start or tracking start-up. temperature monitoring measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation: i d i s ? e v d ? v t or v d ? v t ?in i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor (typically close to 1.0) and i s (satu- ration current) is a process dependent parameter. v t can be broken out to: v t k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmann?s constant. v t is approximately 26mv at room temperature (298k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable tem - perature sensors. the i s term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d ? k q where k d = 8.62 ?5 , and knowing ln(i d /i s ) is always posi - tive because i d is always greater than i s , leaves us with the equation that: v d t kelvin ? k d ?in i d i s
ltm4636 -1 19 46361fa for more information www.linear.com/ltm4636-1 where v d appears to increase with temperature. it is com - mon knowledge that a silicon diode biased with a current source has an approximate ?2mv/c temperature rela - tionship (figure 7), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate ?2mv/c composite diode voltage slope. applications information to obtain a linear voltage proportional to temperature we cancel the i s variable in the natural logarithm term to remove the i s dependency from the equation 1. this is accomplished by measuring the diode voltage at two cur - rents i 1 , and i 2 , where i 1 = 10 ? i 2 ) and subtracting we get: ?v d t(kelvin) ? k d ?in i 1 i s ? t(kelvin) ? k d ?in i 2 i s combining like terms, then simplifying the natural log terms yields: ?v d = t(kelvin) ? k d ? ln(10) and redefining constant k' d k d ?in(10) 198v k yields ?v d = k' d ? t(kelvin) figure 7. diode voltage v d vs temperature t(c) temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 46361 f07 125 solving for temperature: t(kelvin) ?v d k' d ( celsius) t(kelvin) ? 273.15 where 300k = 27c means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected npn transistor at the temp pin can be used to monitor the internal temperature of the ltm4636-1. figure 8. the two images show the ltm4636-1 operating at 1v at 40a and 3.3v at 35a from a 12v input. both images reflect only a 40c to 45c rise above ambient at full load current with 200lpm (8b) (8a) v in v out i out air flow 12 1 40 200 lfm v in v out i out air flow 12 3.3 35 200 lfm
ltm4636 -1 20 46361fa for more information www.linear.com/ltm4636-1 applications information enhanced overvoltage ovp and overtemperature protection otp the ltm4636 -1 has two enhanced protection features that can be used to detect overtemperature and overvoltage. the bias pin is supplied to power the protection circuitry off of an auxiliary supervisory supply separate from the high power circuit breaker path. this is required to properly bias the protection circuitry with the proper headroom at power up, and circuit breaker retry. this separate bias sup - ply needs to supply 1ma per module, and 6ma per module during an overvoltage and overtemperature event. if the crowbar signal is used then an instantaneous current will be need to drive the crow bar mosfets. this is current is ~ 50ma . the bias voltage can be used to program the otp and ovp set points. the tmon pin voltage varies from 1.0v at 25 c up to 1.45v at 150c . the tmon pin can be compared to a program - mable set point utilizing the 24.9k resistor to ground on the otp_set pin. see the block diagram. by adding an external resistor from this pin to the bias pin, an otp trip point can be set below the 150c (1.45v) level as an overtemperature detection, and the over_temp open- collector pin will pull low to provide a system alert, or can be used to trip off power. this feature can be ignored by floating the over_temp and otp_set pins. the equation: r otp 24.9k ? bias otp _ set 1 ; otp _ set 1.0v(25 c) 3.52mv/c ? 105 c for 130c, otp_set = 1.37v where bias is the voltage applied to bias pin, ex : 5v. otp_set is the voltage equivalent to temperature on the tmon pin. for example, bias = 5v, and the overtem - perature trip point is set to 130c. tmon has a range of 440mv from 25 c to 150 c , therefore the tmon pin moves 3.52mv/c above 25c. 130c minus 25c = 105c rise. the rotp resistor calculates out to a close 1% value of 66.5k. the bias supply can be between 4v to 5.5v, the otp_set trip point depends on the bias supply voltage to be accu - rate, otherwise a more accurate reference can be derived from the bias supply to be utilized to program the set point. see application schematics. the ltm4636 -1 controller has overvoltage protection feedback voltage referred that trips at ~7.5% above v out . this feature will try to correct an overvoltage transient issue, but does not protect for a shorted input power source in the event of a top power switch short while the bottom switch is on trying to protect the load. the input source has a direct path to ground in this condition. nei - ther will this feature protect an overvoltage issue caused by an open feedback path. the enhanced overvoltage protection consists of a fast comparator that compares v out to a programmed value set at the ovp_set pin. an ovp_trip point can be set using the bias supply and an external resistor (r ovp ) with the internal 24.9k resistor. the equation: r ovp 24.9k ? bias ovp _ trip ? 1 where ovp_trip is the maximum overvoltage level set point. the ovp_trip open-collector output pulls low and can be used to trip off a circuit breaker or alert the system of an ovp fault. the crowbar output drive can be used to drive an external n-channel power mosfet to clamp the output voltage and discharge the inductor stored energy. depending on the power design, the ovp trip point and the output capacitance, the crowbar clamp may not be needed. testing will need to be performed to characterize the behavior of the clamping with and without the crow - bar. proper crowbar power mosfet soa (safe operating area) selection will be required to make sure the mosfet can handle the discharge current. a small surface mount resistor can be placed in series from v out to the drain of the crowbar fet to limit the crowbar but still clamp the output. to disable the function, float the ovp_set, ovp_trip and crowbar pins. the bias supply can be between 4.0v to 5.5v, while the ovp_trip point depends on the bias supply voltage ac - curacy. otherwise an accurate reference can be derived from the bias supply.
ltm4636 -1 21 46361fa for more information www.linear.com/ltm4636-1 applications information runp and runc enable the runp pin is used to enable the 5v pv cc supply that powers the power driver stage and enables the power stage ~1ms later. the runc pin is used to enable the control section that drives the power stage. the runp needs to be enabled first, and then runc. runp has a 0.85v threshold and can be connected to the input voltage and runc has a 1.35v threshold and a 10k resistor to ground. see the block diagram for details. a 0.1f capacitor from the runc pin to ground is used to set the delay for runc enable. intv cc and pv cc regulators the ltm4636 -1 has an internal low dropout regulator from v in called intv cc . this regulator output has a 4.7f ceramic capacitor internal. this regulator powers the control section. the pv cc 5v regulator supplies power to the power mosfet driver stage. an additional 50ma can be used from this 5v pv cc supply for other needs. the input supply source resistance needs to be very low in order to minimize ir drops when operating from a 5v input source. depending on the output voltage and current, the input supply can source large current,and pv cc 5v regulator needs a minimum 4.7v supply. additional input capacitance maybe needed for 5v inputs to limit the input droop. stability compensation the ltm4636 -1 has already been internally compensated when compb is tied to compa for all output voltages. table 5 is provided for most application requirements. for specific optimized requirements, disconnect compb from compa, and use ltpowercad to perform specific control loop optimization. then select the desired external compensation and output capacitance for the desired optimized response. sw pins the sw pins are generally for testing purposes by moni - toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combina - tion is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance z can be calculated: z(l) = 2fl, where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z(c) = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. a recommended value of 2.2 in series with 2200pf to ground should work for most ap - plications. see figure 19 for layout guidelines. the 2.2 resistor should be an 0805 size. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by jesd51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients in found in jesd51-12 (?guidelines for reporting and using electronic package thermal information?). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulator? s thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are, in and of themselves, not relevant to providing guidance of thermal performance ; instead, the derating
ltm4636 -1 22 46361fa for more information www.linear.com/ltm4636-1 applications information curves provided in this data sheet can be used in a man - ner that yields insight and guidance pertaining to one?s application usage, and can be adapted to correlate thermal performance to one?s own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air ther - mal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as ? still air? although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing pack - ages but the test conditions don?t generally match the user?s application. 3 jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions don ? t generally match the user ? s application. 4 jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure 9; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by je sd51 -12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the device?s total power loss (heat) thermally con - duct exclusively through the top or exclusively through the bottom of the module package?as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package?granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. figure 9. graphical representation of jesd51-12 thermal coefficients 46361 f09 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction a t case (bottom)-to-board resistance
ltm4636 -1 23 46361fa for more information www.linear.com/ltm4636-1 applications information within the ltm4636-1, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity? but also not ignoring practical realities? an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4636-1 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4636-1 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves shown in this data sheet. the power loss curves in figure 10 to figure 12 can be used in coordination with the load current derating curves in figure 13 to figure 18 for calculating an approximate ja thermal resistance for the lt m463 6-1 with various airflow conditions. the power loss curves are taken at room temperature and can be increased with a multiplicative factor according to the junction temperature, which is ~ 1.4 for 120 c . the derating curves are plotted with the output current starting at 40a and the ambient temperature increased. the output voltages are 1v , 2.5v and 3.3v . these are chosen to include the lower, middle and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at ~ 125 c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 125 c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example, in figure 14 the load current is derated to ~ 30a at ~ 94 c with no air flow and the power loss for the 12v to 1.0v at 30a output is about 4.2w . the 4.2w loss is calculated with the ~3w room temperature loss from the 12v to 1.0v power loss curve at 30a , and the 1.4 multiplying factor at 125 c junction. if the 94 c ambient temperature is subtracted from the 125 c junction temperature, then the difference of 31 c divided by 4.2w equals a 7. 4c/w ja thermal resistance. table 2 specifies a 7. 2c /w value which is very close. tables 2, 3, and 4 provide equivalent thermal resistances for 1v , 1.5v and 3.3v outputs with and without airflow and heat sinking. the derived thermal resistances in tables 2 thru 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss curves are provided in figure 10 through figure 12 . the printed circuit board is a 1.6mm thick six layer board with two ounce copper for all layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm . safety considerations the lt m4636 -1 does not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the
ltm4636 -1 24 46361fa for more information www.linear.com/ltm4636-1 applications information figure 10. 5v input power loss curves figure 11. 8v input power loss curves output current (a) 0 watts (w) 8 5 3 6 7 4 2 1 0 25 15 40 35 46361 f10 20 105 30 3.3v out , 500khz 2.5v out , 500khz 1.8v out , 450khz 1.5v out , 425khz 1.2v out , 300khz 1v out , 300khz output current (a) 0 watts (w) 8 5 3 6 7 4 2 1 0 25 15 40 35 46361 f11 20 105 30 3.3v out , 700khz 2.5v out , 600khz 1.8v out , 500khz 1.5v out , 450khz 1.2v out , 400khz 1v out , 350khz output current (a) 0 watts (w) 7 5 3 6 4 2 1 0 25 15 40 46361 f12 20 105 30 35 3.3v out , 750khz 2.5v out , 650khz 1.8v out , 600khz 1.5v out , 550khz 1v out , 350khz ambient temperature (c) 0 load current (a) 45 35 25 40 30 20 15 10 5 0 60 120 46361 f13 4020 80 100 0lfm 200lfm 400lfm 0 45 35 25 40 30 20 15 10 5 0 60 120 46361 f14 4020 80 100 0lfm 200lfm 400lfm ambient temperature (c) load current (a) 0 45 35 25 40 30 20 15 10 5 0 60 120 46361 f15 4020 80 100 0lfm 200lfm 400lfm ambient temperature (c) load current (a) 0 45 35 25 40 30 20 15 10 5 0 60 120 46361 f16 4020 80 100 0lfm 200lfm 400lfm ambient temperature (c) load current (a) 0 45 35 25 40 30 20 15 10 5 0 60 120 46361 f17 4020 80 100 0lfm 200lfm 400lfm ambient temperature (c) load current (a) 0 45 35 25 40 30 20 15 10 5 0 60 120 46361 f18 4020 80 100 0lfm 200lfm 400lfm ambient temperature (c) load current (a) figure 12. 12v input power loss curves figure 13. 5v in , 1v out derate curve figure 14. 12v in , 1v out derate curve figure 15. 5v in , 1.5v out derate curve figure 16. 12v in , 1.5v out derate curve figure 17. 5v in , 3.3v out derate curve figure 18. 12v in , 3.3v out derate curve
ltm4636 -1 25 46361fa for more information www.linear.com/ltm4636-1 table 2. 1v output derating curve v in power loss curve airflow (lfm) ja ( c/w) figures 13, 14 5v , 12v figure 10, 12 0 7. 2 figures 13, 14 5v , 12v figure 10, 12 200 5.4 figures 13, 14 5v , 12v figure 10, 12 400 4.8 table 3. 1.5v output derating curve v in power loss curve airflow (lfm) ja ( c/w) figures 15, 16 5v , 12v figure 10, 12 0 7.4 figures 15, 16 5v , 12v figure 10, 12 200 5.0 figures 15, 16 5v , 12v figure 10, 12 400 4.5 table 4. 3.3v derating curve v in power loss curve airflow (lfm) ja ( c/w) figures 17, 18 12v figure 10, 12 0 7.4 figures 17, 18 12v figure 10, 12 200 5.0 figures 17, 18 12v figure 10, 12 400 4.4 applications information table 5. ltm4636-1 capacitor matrix, all below parameters are typical and are dependent on board layout taiyo yuden 22f, 25v c3216x7s0j226m panasonic sp 470f 2.5v eefgx0e471r sanyo 20sep100m 100f 20v murata 22f, 25v grm31cr61c226ke15l panasonic poscap 470f 2r5 2r5tpd470m5 murata 100f, 6.3v grm32er60j107m panasonic poscap 470f 6.3v 6tpd470m5 avx 100f, 6.3v 18126d107 mat taiyo yuden 220f, 4v murata 220f, 4v
ltm4636 -1 26 46361fa for more information www.linear.com/ltm4636-1 applications information table 6. enhanced external compensation, lower voltage transition during transient. careful power integrity layout required v out (v) c in (ceramic) c in (bulk) ? c out1 (ceramic) and c out2 (ceramic and bulk) c ff (pf) c comp (pf) v in (v) droop (mv) peak-to-peak deviation (mv) recovery time (s) load step (a/s) r fb (k) freq (khz) r comp (k) c comp (pf) 0.9 22f 5 100f 220f 10, 470f 47 100 5, 12 25 50 26 15 10 350 15 1000 1 22f 5 100f 220f 10, 470f 47 100 5, 12 28 55 25 15 7.5 350 15 1000 1.2 22f 5 100f 220f 10, 470f 47 100 5, 12 33 66 30 15 4.99 350 15 1000 ? bulk capacitance is optional if v in has very low input impedance v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) and c out2 (ceramic and bulk) c ff * (pf) c comp (pf) v in (v) droop (mv) peak-to-peak deviation (mv) recovery time (s) load step (a/s) r fb (k) freq (khz) 0.9 22f 5 100f 100f 8, 470f 3 22 100 5,12 38 76 40 15 10 350 0.9 22f 5 100f 220f 6, 470f 2 68 100 5,12 40 80 30 15 10 350 0.9 22f 5 100f 220f 10, 470f none 220 5,12 40 80 30 15 10 350 1 22f 5 100f 100f 4, 470f 3 none 100 5,12 40 80 30 15 7.5 350 1 22f 5 100f 100f 6, 470f 2 none 100 5,12 50 100 30 15 7.5 350 1 22f 5 100f 100f 8, 470f 2 none 150 5,12 55 105 30 15 7.5 350 1.2 22f 5 100f 100f 4, 470f 3 none 100 5,12 45 90 35 15 4.99 350 1.2 22f 5 100f 100f 6, 470f 2 none 100 5,12 45 90 35 15 4.99 400 1.2 22f 5 100f 220f 4, 470f none 100 5,12 50 104 30 15 4.99 400 1.5 22f 5 100f 100f 4, 470f 3 none 100 5,12 60 120 35 15 3.24 425 1.5 22f 5 100f 100f 4, 470f 2 none 100 5,12 56 110 35 15 3.24 425 1.5 22f 5 100f 100f 3, 470f none 100 5,12 75 150 25 15 3.24 425 1.8 22f 5 100f 100f 3, 470f none 220 5,12 90 180 25 15 2.49 500 1.8 22f 5 100f 100f, 470f none 220 5,12 95 197 24 15 2.49 500 1.8 22f 5 100f 220f 2, 470f none 220 5,12 90 180 20 15 2.49 500 2.5 22f 5 100f 100f 2, 470f none 220 5,12 120 220 30 15 1.58 650 (12v) 500 (5v) 2.5 22f 5 100f 100f 6, 470f 22 220 5,12 87 174 40 15 1.58 650 (12v) 500 (5v) 3.3 22f 5 100f 100f 4 220 220 5,12 130 260 25 15 1.1 750 (12v) 500 (5v) 3.3 22f 5 100f 100f, 470f none 220 5,12 140 280 30 15 1.1 750 (12v) 500 (5v) * c ff is a capacitor from v out to v fb .
ltm4636 -1 27 46361fa for more information www.linear.com/ltm4636-1 applications information input voltage will source very large currents to ground through the failed internal top mosfet and enabled internal bottom mosfet. this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the lt m4636 -1 has the enhanced over temperature protection discussed earlier and schematic applications will be shown at the end of the data sheet. layout checklist/example the high integration of the lt m4636 -1 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capacitors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on the pad, unless they are capped or plated over. ? place test points on signal pins for testing. ? use a separated sgnd ground copper area for components connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the comp and v fb pins together. use an internal layer to closely connect these pins together. ? add r snub ( 2.2 ) and c snub ( 2200pf ) to dampen switch ringing. figure 19 gives a good example of the recommended layout. figure 19. recommended pcb layout 1 m l k j h g f e d c b a 2 3 4 5 6 7 v out v out c out1 c in2 c in1 c in4 c in3 c out2 r runc v out gnd temp sense gnd gnd 46361 f19 v in gnd 8 9 10 11 12 c out3 c out4 c run c tk/ss r fb p vcc cap r freq r snub 0805 c snub 0603
ltm4636 -1 28 46361fa for more information www.linear.com/ltm4636-1 figure 20. 10.8v to 14v, 1v at 40a design with protection v in to v out short (zoom in) v in to v out short overvoltage retry with v out at 1.1v typical applications + compa compb track/ss v out sw temp + temp ? snsp1 snsp2 sgnd v in 100pf 5v pv cc c ss 0.1f 22f 1v at 40a 2.2, 0805 0.1f v in 10.8v to 14v 100f 25v 22f 16v 5 optional temp monitor intv cc intv cc ltm4636-1 pv cc pgnd v outs1 + v outs1 ? v fb bias + 470f 6.3v 470f 6.3v + + 470f 6.3v r fb2 7.5k 46361 f20a pins not used in circuit ltm4636: clkout, gmon, pgood, phmode, pwm, test1, test2, test3, tmon 2200pf ovp_set crowbar optional crowbar ovp trip set to 1.1v r ovp 86.6k 0.01f 100k m1 34.8k intv cc pv cc mode/pllin 15k runc runp hizreg bias otp_set over_temp ovp_trip trip freq timer i mon ltc4218-12 gnd intv cc gate m2 si7880dp 5v pg pg 20k 0.1f sense ? source v dd sense + uv overtemperature and overvoltage fault signal 100f 6.3v 4 m1: sud50n03-07 m2: si7880adp 1000pf trip pull uv pin below 0.62v to clear fault uv pin 0.1f 0.01f 10 0.01f 23.7k 1k 66.5k r sense trip = 15mv 0.002 housekeeping supply hot swap circuit breaker front end v in 10k pins not used in circuit ltc4218-12: cl, fb, f lt , i set , ov applied power trip signals pulls uv pin low and retries 100ms later after ovp or otp event. v in = 12v v out = 1v i out = 40a ovp setpoint = 1.1v retry every 100ms v out 1v/div crowbar gate 5v/div switch node 10v/div v in after hot swap circuit breaker 10v/div 100ms/div 46361 f20b v in = 12v v out = 1v i out = 40a short = v in to v out v out 1v/div crowbar gate 5v/div switch 10v/div v in after hot swap circuit breaker 10v/div 100ms/div v in to v out short (zoom in) 46361 f20c v in = 12v v out = 1v i out = 40a short = v in to v out v out 1v/div crowbar gate 5v/div switch 10v/div v in after hot swap circuit breaker 10v/div 100ms/div 46361 f20d
ltm4636 -1 29 46361fa for more information www.linear.com/ltm4636-1 typical applications figure 21. 2-phase 1v, 80a regulator design 7.5k 0.47f 34.8k 4.75v to 15v 4.75v to 15v ++ compa compb track/ss runc runp hizreg freq mode/pllin sw temp + temp ? snsp1 snsp2 sgnd v in 34.8k clk intv cc2 22f 1v 80a 22f 16v 4 c ss 0.22f comp 5v, pv cc2 track/ss runc runp optional temp monitor for telemetry readback ics intv cc intv cc2 5v pv cc2 u2 ltm4636-1 pv cc pgnd v outs1 + v out v outs1 ? v fb v fb r fb2 7.5k 46361 f21 tmon voltage out temp monitor 470f 6.3v 470f 6.3v 100f 6.3v 4 + compa compb track/ss runc runp hizreg phmode freq mode/pllin clkout tmon sw v out temp + temp ? snsp1 snsp2 sgnd v in 22f 2200pf voltage out temp monitor 2.2, 0805 22f 16v 4 v in 5.5v, tie v in and pv cc together, tie runp to gnd. v in > 5.5v, then operate as shown intv cc1 runc runp clk comp track/ss optional temp monitor for telemetry readback ics intv cc intv cc1 5v pv cc1 u1 ltm4636-1 pv cc pgnd v outs1 ? v fb v fb intv cc1 470f 6.3v + 470f 6.3v + 100f 25v 100f 6.3v 4 2200pf 2.2, 0805 sgnd sgnd sgnd sgnd sgnd 100pf pins not used in circuit ltm4636-1 u1: gmon, pgood, pwm, test1, test2, test3, v osns1 + , crowbar, otp_set, ovp_set, bias, ovp_trip, over_temp pins not used in circuit ltm4636-1 u2: gmon, pgood, phmode, pwm, test1, test2, test3, crowbar, otp_set, ovp_set, bias, ovp_trip, over_temp
ltm4636 -1 30 46361fa for more information www.linear.com/ltm4636-1 typical applications figure 22. 3-phase 0.9v at 120a with overtemperature and overvoltage protection + compa compb track/ss runc runp hizreg freq mode/pllin clkout tmon sw temp + temp ? snsp1 snsp2 sgnd v in 34.8k 22f voltage out temp monitor 22f 16v 3 12v intv cc1 runc runp clk comp track/ss optional temp monitor for telemetry readback ics intv cc intv cc1 5v pv cc1 u1 ltm4636-1 pv cc pgnd v outs1 ? v fb v fb 470f 6.3v + 470f 6.3v + 100f 25v 100f 6.3v 3 2.2, 0805 2200pf 4.99k 0.47f + compa compb track/ss runc runp hizreg over_temp freq mode/pllin clkout tmon sw temp + temp ? snsp1 snsp2 sgnd v in 0.9v at 120a clk clk1 intv cc2 22f voltage out temp monitor 34.8k c ss 0.22f 22f 16v 3 comp track/ss runc runp optional temp monitor for telemetry readback ics intv cc intv cc2 5v pv cc2 u2 ltm4636-1 pv cc pgnd v outs1 ? v fb v fb 46361 f22 trip 470f 6.3v + 470f 6.3v r fb3 10k 100f 6.3v 3 100f + compa compb track/ss runc runp hizreg over_temp freq mode/pllin tmon sw v out v out v outs1 + v outs1 ? v outs1 ? v outs1 ? v outs1 ? v out temp + temp ? snsp1 snsp2 sgnd v in 34.8k 22f voltage out temp monitor 22f 16v 3 intv cc3 runc runp clk1 comp track/ss optional temp monitor for telemetry readback ics intv cc intv cc3 5v pv cc3 u3 ltm4636-1 pv cc pgnd v fb v fb bias 5v bias 5v bias 5v otp_set otp_set otp_set trip 470f 6.3v + 470f 6.3v 100f 6.3v 3 12v pins not used in circuit ltm4636-1 u1: gmon, pgood, phmode, pwm, test1, test2, test3, v outs1 pins not used in circuit ltm4636-1 u2: gmon, pgood, phmode, pwm, test1, test2, test3, ovp_set, ovp_trip pins not used in circuit ltm4636-1 u3: gmon, pgood, phmode, pwm, test1, test2, test3, v outs1 , clkout, ovp_set, ovp_trip 2.2, 0805 2200pf 2.2, 0805 2200pf sgnd sgnd sgnd sgnd sgnd sgnd sgnd 100pf ovp_set 66.5k 0.1 1210 102k 5v 66.5k 5v 66.5k 5v v dd sense ? ltc4215gn connector optional circuit breaker front end gate intv cc ss gnd adr0 source sda scl alert on uv gpio fb 10 10k 10nf kelvin sense r s 0.0015 m1 si7880adp 28.7k 3.57k 12v 10k c f 0.01f 34.6k trip 4.53k 12v seatpin system sda scl alert bggnd 12v seatpin sda scl alert bggnd 12v c ss 1nf 0.1f timer c timer 10nf d1 p6ke16a crowbar optional crowbar 0.01f 100k m2 housekeeping supervisory supply over_temp ovp_trip trip
ltm4636 -1 31 46361fa for more information www.linear.com/ltm4636-1 typical applications load current (a) 0 efficiency (%) 95 85 75 90 80 70 65 60 50 60 70 90 100 110 4020 30 80 46361 f25 120 10 46361 f26 v out 40mv droop 30a/s step internal compensation c out = 6 470f 6v tpd pos cap, 12 100f ceramic further optimization can be utilized with external comp v in to v out short v out 1v/div crowbar gate 5v/div switch 10v/div v in after hot swap circuit breaker 10v/div 100ms/div 46361 f27 figure 25. ef?ciency, 12v to 0.9v at 120a figure 26. 12v to 0.9v 30a /s load step figure 27. 12v to 0.9v overvoltage trip figure 23. dc2448a demo board 46361 f24 figure 24. thermal plot, 12v to 0.9v at 120a , 400lfm air flow 46361 f23
ltm4636 -1 32 46361fa for more information www.linear.com/ltm4636-1 typical applications figure 28. 12v to 0.9v, a1/60a with circuit breaker front end and overtemperature and overvoltage protection 46361 f28 1k 0.001 10nf 20k 10k source sense ? sense + gnd gate ltc4218 fb v dd uv ov i mon timer intv cc f lt pg i set pgood 10 m2 psmn2r0-30yle r sense trip = 15mv, 30a kelvin sense 107k 10k 100k trip 10k 7.5k on off aux_uv1 9.53k smbj16a 0.1f 1000pf 0.01f 0.01f 20k input current monitor grn led grn led 9v to 14v input 0.001 10k red led red led in lt1761-5 shdn out byp gnd 0.47f 10f 5v bias + compa compb tk/ss runc runp hizreg ovp_set otp_set otp_set temp + temp ? snsp1 snsp2 sgnd v in 34.8k 22f 100k m1 0.01f 100k voltage out temp monitor 22f 16v 22f 16v 22f 16v 150f 35v 9v to 14v 9v to 14v 9v to 14v intv cc2 runc runp clk2 clk1 comp tk/ss optional temp monitor for telemetry readback ics intv cc intv cc2 5v pv cc2 5v u2 ltm4636 pv cc pgnd v fb v outs1 ? v fb bias pwm2 tp 470f 6.3v + 470f 6.3v 100f 6.3v 3 gnd_sns 2.2, 0805 2200pf 2.2, 0805 2200pf v out + compa compb temp + temp ? snsp1 snsp2 sgnd v in 34.8k 4.99k 5v pv cc1 voltage out temp monitor c ss 0.47f 0.47f trip intv cc1 runc runp clk1 comp optional temp monitor for telemetry readback ics intv cc intv cc1 u1 ltm4636 pgnd v fb v fb pwm1 tp 470f 6.3v r fb 10k + 470f 6.3v 100f 6.3v 3 v outs1 ? v outs1 + 0.9v at 160a + compa compb tk/ss runc runp hizreg tmon pwm sw v out temp + temp ? snsp1 snsp2 sgnd v in 34.8k gnd_sns voltage out temp monitor intv cc3 runc runp clk3 clk2 tk/ss comp optional temp monitor for telemetry readback ics pins not used in circuit u2: pgood, test1, test2, test3, test4, v outs1 , gmon pins not used in circuit u1: pgood, test1, test2, test3, test4, gmon, ovp_temp, ovp_set, crowbar pins not used in circuit u3: pgood, test1, test2, test3, test4, v outs1 , gmon, ovp_temp, ovp_set, crowbar pins not used in circuit u4: pgood, test1, test2, test3, test4, v outs1 , gmon, ovp_temp, ovp_set, crowbar, clkout intv cc intv cc3 u3 ltm4636 pgnd v fb v fb pwm3 tp 470f 6.3v + 470f 6.3v 100f 6.3v 3 gnd_sns 2.2, 0805 2200pf + compa compb tk/ss runc runp hizreg tmon pwm sw v out temp + temp ? snsp1 snsp2 sgnd v in 34.8k voltage out temp monitor intv cc4 runc runp clk3 comp tk/ss optional temp monitor for telemetry readback ics intv cc intv cc4 u4 ltm4636 pgnd v fb v outs1 ? v fb pwm4 tp 470f 6.3v 470f 6.3v 100f 6.3v 3 gnd_sns 2.2, 0805 2200pf 100pf v outs1 ? + 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v phmode freq mode/pllin clkout over_temp 66.5k (130c) 22f 5v pv cc1 5v pv cc bias 66.5k 22f 5v pv cc3 5v pv cc bias 66.5k otp_set 22f 5v pv cc4 5v pv cc bias 66.5k otp_set tmon pwm sw v out v out tmon crowbar pwm sw + runc runp tk/ss sgnd m1: 5ud50n03-07 over_temp ovp_trip trip over_temp trip over_temp trip phmode freq mode/pllin clkout phmode freq mode/pllin clkout phmode freq mode/pllin 0.1 1210 hizreg
ltm4636 -1 33 46361fa for more information www.linear.com/ltm4636-1 typical applications figure 29. dc2448a demo board 46361 f30 46361 f29 load current (a) 0 efficiency (%) 95 85 75 90 80 70 65 60 60 100 4020 80 46361 f32 160 120 140 46361 f34 v out 31mv droop 30a/s step internal compensation c out = 8x 470f 6v tpd pos cap, 16 100f ceramic further optimization can be utilized with external comp v in to v out short v out 1v/div crowbar gate 5v/div switch 10v/div v in after hot swap circuit breaker 10v/div 100ms/div 46361 f31 figure 30. thermal plot, 12v to 0.9v at 160a , 400lfm air flow figure 31. 12v to 0.9v overvoltage trip figure 32. ef?ciency, 12v to 0.9v at 160a figure 33. 12v to 0.9v 30a /s load step
ltm4636 -1 34 46361fa for more information www.linear.com/ltm4636-1 pin id function pin id function pin id function pin id function pin id function pin id function a1 v out b1 v out c1 v out d1 v out e1 pgood f1 snsp2 a2 v out b2 v out c2 v out d2 v out e2 runc f2 snsp1 a3 v out b3 v out c3 v out d3 v outs1 ? e3 track/ss f3 hizreg a4 v out b4 v out c4 v out d4 v outs1 + e4 v fb f4 sgnd a5 v out b5 v out c5 v out d5 compb e5 compa f5 test2 a6 v out b6 v out c6 v out d6 gnd e6 gnd f6 intv cc a7 v out b7 v out c7 v out d7 gnd e7 gnd f7 gnd a8 v out b8 v out c8 v out d8 gnd e8 gnd f8 gnd a9 v out b9 v out c9 v out d9 gnd e9 gnd f9 pv cc a10 v out b10 v out c10 v out d10 over_temp e10 ovp_trip f10 gnd a11 v out b11 v out c11 v out d11 v out e11 crowbar f11 otp_set a12 v out b12 v out c12 v out d12 v out e12 ovp_set f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 gnd k1 gnd l1 gnd m1 gnd g2 gnd h2 test3 j2 gnd k2 gnd l2 gnd m2 gnd g3 clkout h3 mode/pllin j3 gnd k3 gnd l3 gnd m3 gnd g4 sgnd h4 test1 j4 v in k4 v in l4 v in m4 v in g5 freq h5 v in j5 v in k5 v in l5 v in m5 v in g6 gnd h6 v in j6 v in k6 v in l6 v in m6 v in g7 phmode h7 pwm j7 v in k7 v in l7 v in m7 v in g8 runp h8 tmon j8 gnd k8 v in l8 v in m8 v in g9 bias h9 gmon j9 gnd k9 gnd l9 gnd m9 gnd g10 gnd h10 gnd j10 gnd k10 gnd l10 gnd m10 gnd g11 temp ? h11 gnd j11 gnd k11 sw l11 sw m11 gnd g12 temp + h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd package description pin assignment table (arranged by pin number) package row and column labeling may vary among module products. review each package layout carefully.
ltm4636 -1 35 46361fa for more information www.linear.com/ltm4636-1 package description v out v out v out v out v out v out pgood runc snsp2 snsp1 1 2 3 4 5 6 7 top view 8 9 10 11 12 m l k j h g f e d c b a compb test2 crowbar gnd gnd intv cc pv cc phmode runp temp ? temp + bias clkout sgnd sgnd v fb v outs1 + hizreg track/ss compa v outs1 ? freq pwm test3 mode/pllin test1 tmon gmon gnd gnd gnd gnd gnd gnd gnd v in v in v in v in v in gnd gnd gnd sw sw ovp_trip ovp_set otp_set over_temp package photo
ltm4636 -1 36 46361fa for more information www.linear.com/ltm4636-1 package description please refer to http://www.linear.com/product/ltm4636-1#packaging for the most recent package drawings. bga package 144-lead (16mm 16mm 7.16mm) (reference ltc dwg # 05-08-1937 rev d) 4 pin ?a1? corner notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters. drawing not to scale ball designation per jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 144 1016 rev d tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a pin 1 0.0000 0.0000 detail a ?b (144 places) d (3.0) (2.4) (2.4) a detail b package side view z z m x yzddd m zeee 0.630 0.025 ? 144x e b e e b a2 f g bga package 144-lead (16mm 16mm 7.07mm) (reference ltc dwg # 05-08-1937 rev d) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 g f e a b d c h m l k j 2 1 4 3 567 12 891011 7 see notes detail b substrate a1 ccc z // bbb z h2 h1 h3 symbol a a1 a2 b b1 d e e f g h1 h2 h3 aaa bbb ccc ddd eee min 6.57 0.50 2.31 0.60 0.60 0.36 1.95 3.76 nom 7.07 0.60 2.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 2.00 4.06 max 7.42 0.70 2.51 0.90 0.66 0.46 2.05 4.21 0.15 0.10 0.20 0.30 0.15 notes ball ht ball dimension pad dimension substrate thk mold cap ht inductor ht dimensions total number of balls: 144 epoxy/solder (11.20) (10.0) (3.0) module 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 7 package row and column labeling may vary among module products. review each package layout carefully ! b1 mold cap
ltm4636 -1 37 46361fa for more information www.linear.com/ltm4636-1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/17 changed turn-on-time typ from 50ms to 750s 3
ltm4636 -1 38 46361fa for more information www.linear.com/ltm4636-1 linear technology corporation 2017 lt 1217 rev a ? printed in usa www.linear.com/ltm4636-1 related parts design resources typical application part number description comments ltm4609 buck-boost dc/dc module family all pin compatible; up to 5a; up to 36v in , 34v out 15mm 15mm 2.82mm ltm4612 ultralow noise high v out dc/dc module regulator 5a, 5v v in 36v, 3.3v v out 15v, 15mm 15mm 2.82mm package ltm4627 15a dc/dc module regulator 4.5v v in 20v, 0.6v v out 5v, lga and bga packages LTM4620 dual 13a, single 26a dc/dc module regulator up to 100a with four in parallel, 4.5v v in 16v, 0.6v v out 2.5v ltm4636 ltm4636-1 without overvoltage/overtemperature protection 4.75v v in 15v, 0.6v v out 3.3v, 16mm 16mm 7.12mm bga 5v to 2.5v at 30a design subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technology?s family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. compa compb tk/ss runc runp hizreg freq mode/pllin tmon v out temp + temp ? snsp1 snsp2 sgnd v in 15k 47k c ss 0.1f 22f 2.5v at 35a voltage out temp monitor 0.1f 22f 16v 22f 16v 22f 16v 22f 16v 22f 16v 5v 100f 25v intv cc optional temp monitor for telemetry readback ics intv cc intv cc ltm4636-1 pv cc pgnd v outs1 + v outs1 ? v fb + 470f 4v 470f 4v + + r fb 1.58k 100f =3 6.3v 47pf 46361 ta02 sgnd sgnd sgnd pins not used in circuit ltm4636-1: clkout, gmon, pgood, phmode, pwm, sw, test1, test2, test3, crowbar, bias, ovp_set, otp_set, over_temp, ovp_trip

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